This invention relates to means for forcing a storage device to a selected logical state. This is useful for, among other things, quickly placing a predetermined word in the output registers of memory circuitry.
In the operation of certain microprocessor based digital circuitry, it is sometimes necessary to have the capability to force certain registers to selected values regardless of the stage of operation of the circuit. This capability is useful, for example, upon system start-up, restarting the system after power interruptions, and user initiated reinitialization of the computer system.
A circuit commonly used as a register is the D-type flip-flop or bistable multivibrator. A D-type flip-flop receives a data input signal and provides the equivalent of that input signal on an output terminal, and provides this output signal until a new data input signal is stored during a subsequent clock period. FIG. 1 is a schematic diagram of a prior art master-slave D-type flip-flop 30 which includes an initialize function. Master flip-flop 10 receives input signal D from input terminal 71 when the clock input signal CLK on clock input terminal 77 is a logical 0 (approximately 0 volts). The emitters of transistors 79 and 80 are connected to clock input terminal 77. The highest voltage level possible on the bases of transistors 79 and 80 is a logical 1 (approximately 5 volts). Therefore, when clock input signal CLK is a logical 1, transistors 79 and 80 are not forward biased. When clock input signal CLK is a logical 0, transistors 79 and 80 turn on if bias is provided to the bases of transistors 79 and 80, respectively.
A logical 1 input signal D on input terminal 71 is inverted once by NPN transistor 69, thus providing a logical 0 on the collector of transistor 69. This logical 0 on the collector of transistor 69 is applied to the base of NPN transistor 74, thus providing a logical 1 on the collector of transistor 74. The logical 0 on the collector of transistor 69 causes current to flow from positive voltage source V20, through resistor 82, base-emitter junction 78-2, diode 75, and transistor 69 to ground (approximately 0 volts). Because transistor 74 is off, no current flows from positive voltage source V20, through resistor 83, base-emitter junction 81-2, diode 76, and transistor 74 to ground. Because base-emitter junction 78-2 is forward biased, the collector of transistor 78 is pulled low, and thus the base of transistor 79 is low, thereby keeping transistor 79 off. Therefore, bias is not provided to the base of transistor 79 and transistor 79 is off even when clock signal CLK applied to clock input terminal 77 is a logical 0. Base-emitter junction 81-2 is not forward biased because transistor 74 is off. Base-emitter junction 81-1 is not forward biased because transistor 79 is off. Therefore, when clock signal CLK applied to clock input terminal 77 is a logical 0, current flows from positive voltage source V20, through resistor 83, the base-collector junction of transistor 81, and the base-emitter junction of transistor 80 to clock input terminal 77. Therefore, transistor 80 is on when clock signal CLK applied to clock input terminal 77 is a logical 0 and input signal D is a logical 1.
When transistor 80 is on, current flows from positive voltage source V20 through resistor 87, the base-emitter junction of NPN transistor 86, and transistor 80 to clock input terminal 77. Therefore, transistor 86 is on and the collector of transistor 86 provides a logical 0 to the base of transistor 85, thereby causing transistor 85 to be turned off. Furthermore, because transistor 79 is off, no current flows from positive voltage source V20, through resistor 88, and the base-emitter junction of transistor 89. Therefore, current flows from positive voltage source V20 through resistor 88, the base-collector junction of transistor 89, the base-emitter junction of transistor 90, and resistor 92 to ground. The voltage drop thus developed across resistor 92 forward biases transistor 93, thereby turning on transistor 93. With transistor 93 turned on, the base of transistor 99 is pulled to a logical 0, thereby turning off transistor 99. With transistor 99 turned off, output terminal 103 is pulled up by resistor 100, thereby providing a logical 1 output signa D.sub.out on output terminal 103. Furthermore, with transistor 93 turned on, the logical 0 signal on the collector of transistor 93 is applied via forward biased diode 96 to the base of transistor 85. Thus, transistor 85 is turned off, which in turn does not pull down the base of transistor 90. With the base of transistor 90 remaining a logical 1, the output signal D.sub.out remains a logical 1 even when clock input signal CLK switches to a logical 1.
Conversely, when a logical 0 input signal D is placed on input lead 71, transistor 79 is turned on and transistor 80 is turned off, when clock input signal CLK on clock input terminal 77 is a logical 0. Because transistor 79 is on, transistor 89 does not provide bias to transistor 90. Therefore, transistor 90 is off, transistor 93 is not forward biased, and thus transistor 93 is off. Because transistor 93 no longer pulls the base of transistor 99 to ground, transistor 99 is on. Therefore, the output signal D.sub.out on output node 103 is a logical 0. Because transistor 93 is off and because transistor 80 is off, transistor 85 is forward biased by transistor 86. When transistor 85 is on, the base of transistor 90 is a logical 0. Therefore, the output signa D.sub.out on output terminal 103 remains a logical 0 when clock input signal CLK switches to a logical 1, until the status of slave flip-flop 20 is altered by the master flip-flop 10 during the logical 0 cycle of clock input signal CLK applied to clock input terminal 77.
Transistor 105, diode 107, resistor 108, and initialization terminal 104 form an initialization input circuit. When a logical 1 initialization input signal I is placed on initialization input terminal 104, NPN transistor 105 is turned on and the collector of transistor 105 provides a logical 0 to the base of transistor 69 regardless of the status of input signal D, thereby forcing output signal D.sub.out on output terminal 103 to a logical 0 when clock signal CLK becomes a logical 0. However, it is desirable to have an initialization circuit which alters output signal D.sub.out asynchronously (i.e., without regard to the state of the clock signal CLK). The prior art circuit of FIG. 1 does not alter output signal D.sub.out until clock signal CLK applied to clock input terminal 77 becomes a logical 0. In addition, it is desirable to have the capability to program the asynchronous initilization circuit to programmally provide either a logical 1 output signal or a logical 0 output signal in response to an initialization input signal.